1. Field of Invention
The present invention generally relates to a method for manufacturing a semiconductor structure, and more particularly, to a method for manufacturing a high-performance semiconductor structure by a stress memory technique.
2. Description of Related Art
It is well known that performance of a field effect transistor (FET) may be improved when stress is applied thereto. In such a case that stress is applied to a field effect transistor, tensile stress may increase mobility of electrons, and thus driving current of an nFET, while compressive stress may increase mobility of holes, and thus driving current of a pFET.
One approach for providing such stress is referred to as Stress Memorization Technique (SMT), which comprises forming a material having intrinsic stress, such as silicon nitride, at various locations of a semiconductor structure, for example, above a channel region; performing annealing so that the stress is memorized at the respective locations, such as a gate region or an extension region; and removing the material having the stress. Thus, the stress remains and increases mobility of electrons or holes, which in turn enhances overall performance of the semiconductor structure.
One of the problems with the SMT is that it may only be applied to nFETs. In particular, annealing should be performed so as to memorize the stress in the semiconductor structure, typically at a high temperature. However, those materials used for applying the stress to the field effect transistor, such as nitride, may only provide tensile stress at the high temperature. Consequently, the application of SMT may be limited to nFETs.
In view of the above problem, there is a need for SMT which may be used in pFETs.